To provide a reliable up/down counter with a simple circuitry without using an external clock.

The up/down counter device 10 outputs an up/down state signal (C) from two-phase pulse signals (A), (B) input to an up/down decoder 12 and generates a decoder pulse signal (D) synchronized with each of change points of the two-phase pulse signals. The decoder pulse signals are doubled in an EXOR gate 14 and the doubled pulse signals (E) are logically added to the up/down state signal in an AND gates 18, 20, to generate an up pulse signal (F) and a down pulse signal (G). The signals are counted in built-in hardware counters 22a, 22b of a CPU 22 in advance and thereafter are calculated at constant intervals in a software processor 22c.