To sufficiently derive the performance of an IC circuit and to decide the final value of a counter fast by eliminating the influence of a propagation delay time transmitted from a counter-side IC to a decision-side IC.

The multi-chip type counter final value decision circuit stores a main down counter 202 which cannot put in an original LSI 100 in another LSI 200 and transmits a main zero detection signal A of the counter 202 to the original LSI 100 to decide the zero value of the counter 202. A main zero detecting circuit 201 of the counter 202 provided in the LSI 200 is so constituted as to ignore the low-order one bit LSB of the counter 202. A low-order one-bit counter 102 is built in the original LSI 100 and a sub zero detecting circuit 101 for the subcounter 102 is arranged. The original LSI 100 is provided with a gate 104 which ANDs a sub zero detection signal B and the main zero detection signal A and applies the result to a sequencer 103. Even when the main zero detection signal A is applied to the gate 104 a propagation delay time later, a whole zero detection signal C matching the sub zero detection signal B having no propagation delay time delay is applied to the sequencer 103 to substantially eliminate the propagation delay time.