To provide a counter capable of high-speed counting without increasing a circuit scale.
In the counter 41 incorporated in a laser scanning type optical measurement apparatus, low-order bit data D0-D2 are generated in a phase split system, and intermediate bit data D3 and high-order bit data D4-D15 are generated in a single phase system. A low-order bit data generating section 61 is provided with four flipflops in a first stage in which clock signals CK1-CK4 having phases different from one another are added to a clock input, and four flipflops of a second stage. The low-order bit data generating section 61 causes a selector circuit SEL to select values 0-4 to be acquired in an adding circuit ADD and values 5-7 to be acquired in a subtracting circuit SUB to acquire 0-7 being low-order bit data D0-D2.
KUWAJIMA MAMORU
KOMEHANA TAKASHI
| JPH03141716A | 1991-06-17 |
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