To reduce a circuit scale forming an entire circuit by inputting a signal directing the value preceding by one to the first value and a signal directing the value next to the last value by two AND gates to a flip flop circuit.

A signal A8, directing the first value to output a signal specifying between from a certain value (the first value) to another certain value (the last value), and a signal A105 specifying the value next to the last value are generated in two 8-input AND gates 2, and the signal A8 is inputted to the set (S) terminal of the RS flip flop circuit 4, and the signal S105 is inputted to a reset (R) terminal. The RS flip flop circuit 4 is a flip flop device, having the set terminal S and the reset terminal R, and if a signal of logic H is added to the S terminal, thereafter its output Q holds the state of logic H, while if the signal of logic H is added to the R terminal, thereafter, the output Q holds the state of logic L. When the S terminal and the R terminal simultaneously turn to logic H, the input to the R terminal is prioritized.