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Title:
COUNTER OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2009278604
Kind Code:
A
Abstract:

To provide a counter, which reduces propagation time delay of the counter and minimizes data skew.

An n-bit counter includes n counter blocks each including: a D-flipflop; a second MUX which selects any one of external data and a second output signal of the D-flipflop in response to a data load signal and outputs a selected signal; and a first MUX which transfers any one of a first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal. Here. an mth counter block outputs an mth bit signal, which is toggled in a period where all output signals of second MUXs included in first to (m-1)th counter blocks are at a first level and the counter enable signal is at a second level.


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Inventors:
LIM SANG OH
JEONG BYOUNG KWAN
YOON MI SUN
Application Number:
JP2008206663A
Publication Date:
November 26, 2009
Filing Date:
August 11, 2008
Export Citation:
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Assignee:
HYNIX SEMICONDUCTOR INC
International Classes:
H03K23/00; H03K23/40
Domestic Patent References:
JP2008305947A2008-12-18
JP2000243041A2000-09-08
JP2000132921A2000-05-12
JP2000200467A2000-07-18
Foreign References:
WO2005027112A12005-03-24
US20020194548A12002-12-19
US20030154434A12003-08-14
US20070075732A12007-04-05
US20070198101A12007-08-23
Attorney, Agent or Firm:
Nakagawa International Patent Office



 
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