PURPOSE: To facilitate the reduction in the number of control pins for testing, the reduction in the number of test patterns and the design of the test pattern by controlling the carry of a counter in counter test.

CONSTITUTION: A carry holding circuit 6 receives and holds a carry signal 9 outputted from a counter 1. A counter test control circuit 4 selects the carry signal 9 at the usual time in accordance with a test control signal 15 and at the time of the counter test, a carry holding output 10 outputted from the carry holding circuit 6 is selected and inputted to an enable pin 11 of a counter 2. In the same manner, a carry holding circuit 7 receives and holds a carry signal 12. A counter test control circuit 5 selects a carry holding output 13 at the time of the counter test in accordance with the test control signal 15 and inputs it to the enable pin 14 of a counter 3.