PURPOSE: To realize an n-bit counter with preset in which the number of input terminals are reduced to a minimum by detecting the rise or fall of a signal inputted to the input terminal, and outputting a loading signal to the n-bit counter after the lapse of bits ≥(n).

CONSTITUTION: When the preset data of (n) bits converted to serial data is inputted to the input terminal 11 in a state where a shift register 1 is enabled, the preset data is stored in the shift register 1, and the preset data is inputted to the preset data input terminal 4 of the counter 2 with preset. Meanwhile, a loading signal delay circuit 13, in the case of detecting the rise of the input terminal 11, the loading signal is outputted to the counter 2 with preset after the lapse of time of the bits ≥(n) after the rise is detected. A preset operation can be performed since the preset data inputted from the input terminal 11 is inputted to the preset input terminal of the counter 2 with preset.