Title:
カウンタ
Document Type and Number:
Japanese Patent JP3567309
Kind Code:
B2
Abstract:
A counter operated on the 2-phase clock which divides a lag time occurring in shift circuits into two parts, one being on the basis of a first clock and the other being on the basis of a second clock, the lag time in each part being independently accumulated so as to diverge the lag time, thereby speeding up the operation of the counter.
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Inventors:
Hiromichi Miura
Application Number:
JP10559696A
Publication Date:
September 22, 2004
Filing Date:
April 25, 1996
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G06F7/00; H03K23/42; (IPC1-7): G06F7/00
Domestic Patent References:
| JP58105348A | ||||
| JP60110026A | ||||
| JP2259926A | ||||
| JP5020026A |
Attorney, Agent or Firm:
Nobuo Kono