PURPOSE: To preferentially execute a load operation by taking the logic of a clear pulse and a load pulse and supplying its output to a clear terminal to reverse virtually the priority of a clear operation and the load operation.

CONSTITUTION: To a quinary counter, '3' is preset, when a load pulse PL is supplied to a load terminal LD. A count value output terminal Q2 is connected to one input terminal of a NAND circuit 52 through inverters 41, 51 for decoding '4'. Also, the load terminal LD to which the load pulse PL is supplied is connected to the other input terminal. Its output is connected to a clear terminal CLR. When each timing of a clear pulse PC and the load pulse PL has coincided, an output P'C of the NAND circuit 52 supplied to the clear terminal CLR becomes an H level, and a clear operation is not executed but a load operation is preferentially executed.