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Title:
UP/DOWN COUNTER
Document Type and Number:
Japanese Patent JPH05284009
Kind Code:
A
Abstract:

PURPOSE: To eliminate the need for the operation and excess terminals of a counting direction designating flag based on an instruction by discriminating a counting direction according to the state of a clock line signal and adding a level width detecting circuit or a duty ratio detecting circuit.

CONSTITUTION: An external input terminal 4 is a terminal for inputting external counting clocks, and a level width detecting circuit 2 designates the counting direction based on the level width of the external counting clock. When the high level of the inputted eternal counting clock longer than a certain time is detected, a counting direction designating flag 1 is set and when the low level width is detected, the counting direction designating flag 1 is cleared. Then, the set value is outputted to a counter 3. By the output of the counting direction designating flag 1, the counter 3 designates either up-count or down- count and based on the continuously inputted valid edge, the counting operation is performed. Thus, since the counting direction is designated by the input method of the counting clock itself, program space or program executing time is saved.


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Inventors:
Teruo Ichimura
Application Number:
JP7966792A
Publication Date:
October 29, 1993
Filing Date:
April 01, 1992
Export Citation:
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Assignee:
NEC IC Microcomputer System Co., Ltd.
International Classes:
H03K21/00; H03K23/00; (IPC1-7): H03K21/00; H03K23/00
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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