PURPOSE: To offer the counting circuit which can decrease the necessary number of flip-flops.

CONSTITUTION: Four D type flip-flops 1-4 are cascaded in stages so as to count 10 pulses of a specific clock signal CLK. Respective inverted outputs QN and D inputs of the respective flip-flops are connected mutually and the clock signal CLK is supplied to the clock input of the flip-flop in the 1st stage. A clock input terminal of an ith-stage flip-flop 2≤i≤n and an inverted output QN of an (i-1)th-stage flip-flop are connected to each other. The outputs Q of the 2nd-stage and 4th-stage flip-flops 2 and 4 are supplied to an AND gate 5 and the output of the AND gate 5 is inverted, the counting of 10 pulses is completed. A logical value indicating the completion of the counting is held by latch circuits 6 and 7.