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Title:
ADDITION/SUBTRACTION COUNTING CIRCUIT
Document Type and Number:
Japanese Patent JPS6338327
Kind Code:
A
Abstract:

PURPOSE: To perform accurate addition and subtraction even with these signals inputted at a time by using a set/reset circuit which is set by one of two output signals of an overlap eliminating circuit and then reset by the other output signal.

CONSTITUTION: This counting circuit includes the 1st synchronizing differention circuit 2 which works at the leading edge of a clock, the 2nd synchronizing differention circuit 3 which works at the trailing edge of the clock, an overlap eliminating circuit 4 which eliminates an overlap part of two output signals of both differention circuits 2 and 3, a mixing circuit 5 which mixes two output signals of the circuit 4, a delay circuit 6 which delays the output of the circuit 5, a set/reset circuit 7 which is set by one of two output signals of the circuit 4 and then reset by the other output signal, and an up/down counter circuit 8 which has an addition/subtraction switching function. Thus two input signals if supplied at a time are accurately counted.


Inventors:
UEDA EIJI
OKAMOTO HIROSHI
Application Number:
JP18292586A
Publication Date:
February 18, 1988
Filing Date:
August 04, 1986
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03K23/00; G01D5/244; G01D5/245; H03K21/02; H03K23/86; (IPC1-7): H03K21/02; H03K23/86
Attorney, Agent or Firm:
Toshio Nakao



 
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