To provide a counting device which satisfies fail safe counting performance not performing rash counting output in a failure time, and is excellent in reliability.

The device comprises a counter 100 which generates an output, when counting of input clock signals CK reach to a determined value, after a preset signal/PRESET presets fully dividing circuits A1 to An; a falling detection circuit 101 which detects reset by detecting falling of the counter output; a self-hold circuit 102 which outputs a reset confirmation signal, if the reset detection signal of the falling detection circuit 101 is input; a rising detection circuit 103 which detects rising of the counter output; and a self-hold circuit 104 which generates an effective counting result output, when the rise detection signal is input from the rising detection circuit 103 during the generation of the reset confirmation signal.