Title:
分周器回路
Document Type and Number:
Japanese Patent JP4977717
Kind Code:
B2
Abstract:
A circuit for deriving an output clock signal from an input clock signal, the output clock signal having a frequency which is 1/Nth of the frequency of the input clock signal, where N is an odd number. The circuit comprises a plurality of latches configured as a latch ring, the latches being arranged in successive pairs, each pair of latches comprising a first latch that switches on one of the rising or falling edge of the input clock signal, and a second latch that switches on the other of the rising or falling edge of the input clock signal. An RS flip flop is coupled to receive at one of its set and reset inputs an output from the latch ring that is switched on a rising edge, and at the other of the set and reset inputs an output from the latch ring that is switched on a falling edge. Said output clock signal is provided at an output of the RS flip flop.
Inventors:
Mirror, robin, james
Application Number:
JP2008550855A
Publication Date:
July 18, 2012
Filing Date:
January 15, 2007
Export Citation:
Assignee:
Future Waves UK Limited
International Classes:
H03K23/48; H03K23/54; H03K23/66; H03K23/70
Domestic Patent References:
| JP10261953A |
Attorney, Agent or Firm:
Keiichiro Saikyo
Takeshi Sugiyama
Takeshi Sugiyama