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Patent Searching and Data


Title:
CPU FAULT PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JPH03276245
Kind Code:
A
Abstract:

PURPOSE: To carry on the information processing even with the faults occurred in an input/output device and at the interface part between the input/output device and a channel by providing a working-alternate address table for the input/output device and a fault flag corresponding to each input/output device.

CONSTITUTION: The fault flags are simultaneously set to the working and alternate addresses. These flags are set at 1 by a report received from an input/ output device and the fault occurred at an interface part between the input/ output device and a channel. Then the fault flags are reset at 0 by a hardware reset instruction. meanwhile the working and alternate addresses are set on the address tables 3 and 4 in a preparation end state of a CPU. Then a working address is exchanged with an anternate address at execution of the hardware reset instruction and with the fault flag set at 1. Thus the system down is automatically recovered despite a fault occurred in an input/output device or at an interface part between the input/output device and a channel.


Inventors:
YAMANO SHUICHI
IWAO HIDEKI
Application Number:
JP7330290A
Publication Date:
December 06, 1991
Filing Date:
March 26, 1990
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F11/20; G06F13/00; (IPC1-7): G06F11/20; G06F13/00
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)