Title:
CPU HAVING INTEGRATED MULTIPLICATION/ACCUMULATION UNIT
Document Type and Number:
Japanese Patent JPH06208456
Kind Code:
A
Abstract:
PURPOSE: To provide a multiplying/accumulating function in a short clock cycle.
CONSTITUTION: A system memory 108 for storing data, a bus interface mechanism 110 provided in a CPU, and a system bus 106 which connects between arithmetic means, such as multiplication/accumulation units 104, etc., which perform arithmetic processing on retrieved data are provided and the CPU manages its internal register 112 used when the arithmetic means retrieve data in response to a program instruction specified by the CPU. The arithmetic means performs multiplication of two binary numbers with codes by using a corrected booth algorithm and, when the means perform the multiplication, reducing the cycle time and hardware conditions.
Inventors:
RARUFU DABURIYU HAINZU
GEIRII DEI FUIRITSUPUSU
DONARUDO KEBIN KOBII
TOOMASU DABURIYU ESU TOMUSON
GEIRII DEI FUIRITSUPUSU
DONARUDO KEBIN KOBII
TOOMASU DABURIYU ESU TOMUSON
Application Number:
JP14731792A
Publication Date:
July 26, 1994
Filing Date:
June 08, 1992
Export Citation:
Assignee:
NAT SEMICONDUCTOR CORP
International Classes:
G06F7/533; G06F7/52; G06F7/53; G06F7/544; G06F9/38; G06F12/08; (IPC1-7): G06F7/52; G06F12/08
Attorney, Agent or Firm:
Kazuo Kobashi (1 person outside)
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