PURPOSE: To reduce a circuit scale and simplify transfer control considerably by controlling the CPU so that when one memory is in a write mode, the other memory is in a read mode to prevent the occurrence of lacing.

CONSTITUTION: In a period of time when CPU 1 keeps a switch signal W/R at high level, a selector 3 connects a RAM 5 to the address bus of the CPU, and a selector 4 connects a RAM 6 to the address bus of an address counter. On the other hand since the RAM 5 is in a write mode, it reads, in accordance with an output address signal of address counter 2, CPU data that was written in the RAM 5 precedently and sends the CPU data read out to the data bus of CPU. Since a selector 7 selects the data bus at the side of RAM 6, the read out CPU data is sent out to the multiplexer apparatus via a parallel/serial converter 8.