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Patent Searching and Data


Title:
CPU STOP MONITORING SYSTEM
Document Type and Number:
Japanese Patent JPH03154938
Kind Code:
A
Abstract:

PURPOSE: To prevent the misrecognition of the CPU stop at normal working of the CPU by outputting a fact that the CPU has the overflow and stops after a counter worked for a fixed time if no interruption answer signal is sent back to the counter from the CPU.

CONSTITUTION: A counter C starts its counting action again every time the counter is reset by an interruption answer signal 3. Then an interruption is applied to a CPU A from a flip-flop B in timing T25. If the CPU A sends back no signal 3 to an answer, the counter C working at the rise of a clock 1 has the overflow at T26 later than T25 by a fixed time and outputs a signal via a signal line 4 to show that a CPU of a device is stopped. Thus, it is possible to prevent the misrecognition of the CPU stop even though the CPU A is nor mally working.


Inventors:
SHIBAZAKI KAZUISA
Application Number:
JP29467289A
Publication Date:
July 02, 1991
Filing Date:
November 13, 1989
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/30; (IPC1-7): G06F11/30
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)