Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
CPU SUPERVISORY CIRCUIT
Document Type and Number:
Japanese Patent JPS61255445
Kind Code:
A
Abstract:

PURPOSE: To self-return the temporary abnormal action due to a noise, etc., by outputting a signal to show the normal action from a CPU itself to the external part, making it to a prescribed time stop condition when a normal action signal is not outputted due to the abnormal occurrence and executing the restarting.

CONSTITUTION: An output signal (e) of a latch circuit 4 is a high level and a CPU 1 is a normal action, and then, an output signal (d) of the second timer 3 is a high level, the first timer 2 is reset by an ordinary action signal (a) of the CPU 1 and started, and since the first timer period T2 is larger than the ordinary action signal (a) period T1, a pulse signal (c) is not outputted. After the first timer 2 is reset, when the tie T1 does not pass, abnormality is generated at the CPU 1, and then, after the time T2 passes from when the first timer 2 is finally reset, the pulse signal (c) is outputted, a latch circuit 4 comes to be a low level, the CPU 1 is reset and comes to be the stop condition, the second timer 3 is started, after the prescribed time passes, a pulse signal (d) is outputted and the CPU 1 is restarted.


Inventors:
INOUE AKIRA
Application Number:
JP9713585A
Publication Date:
November 13, 1986
Filing Date:
May 08, 1985
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
G06F11/30; G06F11/00; (IPC1-7): G06F11/30
Attorney, Agent or Firm:
Uchihara Shin