To deal with a fault or bugging in the arbitrary number of instructions when the instructions are stored in a ROM which is difficult for rewriting.
The second ROM stores information showing the address of a first ROM 201 where the instruction is to be replaced with a substitutive routine and the DMA transfer of this substitutive routine in the second ROM to a second RAM is performed. A first RAM 202 stores the substitutive information of one bit showing whether the instruction in the address of the first ROM 201 is a fault or bugging corresponding to that address, and that information is outputted to a select terminal SEL of a selector 204 as a select signal PD. A register 203 outputs the instruction of a trap command to the selector 204 and when the select signal PD is high, the selector 204 selects the output signal of the first ROM 201 but when the signal PD is low, the selector selects the trap instruction of the register 203.
INOUE YOSHITSUGU
NORO TORU
ISHII TOMOKI
