PURPOSE: To shorten a CRC detection time by providing the CRC (cyclic redundancy check) detecting circuit with a 1st shift register for successively shifting a CRC computed result by a time slot, and outputting the delayed signal and a 2nd shift register for delaying the input data of the CRC computed result by one multiframe.

CONSTITUTION: Data selected from the CRC computed result of one multiframe data A and data deleyed by 8 to 1 time slots through a shift register 13 so that the delay time of each multiframe input is successively reduced in each time slot are applied to one inputs of comparators 15, 16 and data B successively inputted in each multiframe and data SB obtained by delaying the data B by 8 time slots through a shift register 12 are applied to the other inputs of the comparators 15, 16 to compare respective data. Since the CRC detection of all phase relation to be obtained between both the data A, B is executed, the gate size can be reduced and the detection time can be shortened.