PURPOSE: To simplify the circuit and to speed up the operation time, by using a plurality of data buffer registers and a parity check circuit checking the normality of the registers and making partial parallel operation of the cyclic redundancy check.

CONSTITUTION: Normally, an input signal is inputted to data buffer registers REG0, REG1 via gate circuits GE0, GE1, the content is respectively checked at parity check circuits PCC1, PCC2, and the result is obtained from an output line P. C. The data from each terminal is sequentially assembled for the characters at a communication controller, and a data is read out on an input line IN every time one character is assembled. In this case, from a storage device MEM, the information BCC as the result of CRC operation is read out corresponding to lines. A prescribed operation is made via circuits PCC1, 2, correction circuit AC, and circuits GE0, GE1, and the result in stored again in a location corresponding to the line of the device MEM. This processing is repetitively made each line and the normality of the resultant data can be checked.