To reduce power consumption of a cumulative addition circuit.

The cumulative addition circuit includes an addition circuit, a counter, and a clock gating control circuit. The addition circuit performs cumulative addition of data of prescribed bits, and activates a carry signal when a carry occurs. The counter performs a countup when the carry signal is activated, and outputs a count value of N bits as an upper digit of a cumulative addition result. The counter includes an N-bit register latching each bit of the count value. A register holding bits having a value changing according to the activation of the carry signal is an active register. The clock gating control circuit receives the carry signal from the addition circuit, and receives the count value from the counter. The clock gating control circuit activates only clock supply to the active register by referring to the count value received from the counter, and deactivates clock supply other than that.