Title:
CURRENT MIRROR AMPLIFIER FOR INSULATED GATE FIELD-EFFECT TRANSISTOR PROVIDED WITH NESTED CASCODE INPUT/OUTPUT STAGE
Document Type and Number:
Japanese Patent JP2620528
Kind Code:
B2
Abstract:
PURPOSE: To provide a current mirror amplifier provided with an IGFET nest cascode input/output stage without needing a semiconductor junction by which a potential is floated to/from an integrated circuit board.
CONSTITUTION: FETs Q11 and Q12 are connected in nest cascode to each other at the input end of this current mirror amplifier, and the FETs Q13 and Q14 are in nested cascode connection with each other at an output end. The drains of the FETs Q12 and Q14 are respectively connected to the input terminal and output terminal of the current mirror amplifier and the sources of the FETs Q11 and Q13 are connected to the common terminal of the current mirror amplifier. The potential at the input terminal of the current mirror amplifier is impressed to the mutual connection of the gate electrodes of the FETs Q11-Q14 and the operation of the current mirror amplifier is executed. The source-gate voltage of the FET Q11 exceeds the source-gate voltage of the FET Q12 in response to the serial transmission of a current through the respective channels and the source-gate voltage of the FET Q13 exceeds the source-gate voltage of the FET Q14 in response to the serial transmission of the current through the respective channels.
Inventors:
Allen Leroy Limburg
Application Number:
JP30931994A
Publication Date:
June 18, 1997
Filing Date:
December 13, 1994
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H03F3/343; G05F3/26; H03F3/345; H03F3/45; (IPC1-7): H03F3/343; G05F3/26
Domestic Patent References:
| JP1106607A | ||||
| JP1284005A | ||||
| JP1202012A |
Attorney, Agent or Firm:
Tadahiko Ito (1 outside)
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