To generate continuous cycles with high resolution by receiving the output of a VCO at a DDS, applying this output to the other phase comparison input terminal of a PLL for transmission.

In a PLL circuit 60, a phase-locked loop is controlled by a phase comparator 20, so that the phase of an output signal from an external reference clock generator 10 matches the phase of an output signal from a DDS 30. As a result, in the locked state of the PLL 60, an output signal fs of the reference clock generator 10 is equal to a frequency fb of the output signal from the DDS 30. The clock frequency fb of the output from the DDS 30 can be generated at high-resolution pitches and further, even when this setting is switched, continuity in the phases of output waveforms is kept. Thus, an output period Tout of the PLL circuit 60 can be set with a (1/2n) resolution of a period T for a reference period generator 10.