Title:
CYCLIC REDUNDANCY CHECK/CALCULATION METHOD AND DEVICE THEREOF
Document Type and Number:
Japanese Patent JP3231713
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent processing efficiency from deteriorating due to a read wait time of an initial value.
SOLUTION: A cyclic redundancy check calculation circuit 1 sets an initial value of zero, checks and calculates transfer data 100 for once to thrice value of m and stores the result to an intermediate result register 2. A transfer number calculation circuit 41 calculates the number (m) of data transfer and provides an output. After receiving an initial value 101, halfway result calculating circuits 51, 52 conduct halfway calculation based on the initial value 101. Selection circuits 31, 32 select the initial value 101 or outputs of the halfway result calculating circuits 51, 52, depending on whether or not an outputted transfer circuit (m) is a mode 2 equals or 1. An exclusive OR 8 calculates the output of the selection circuit 32 and an output of the intermediate result register 2 to output a calculation result 9 of the device. Since calculation is started before the inputting of the initial value 101, processing time is reduced.
Inventors:
Takahisa Hashimoto
Application Number:
JP27127398A
Publication Date:
November 26, 2001
Filing Date:
September 25, 1998
Export Citation:
Assignee:
Kofu NEC Corporation
International Classes:
H03M13/00; H03M13/09; H04L12/28; (IPC1-7): H03M13/09; H04L12/28
Domestic Patent References:
| JP6311049A | ||||
| JP7240739A | ||||
| JP964754A |
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)