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Title:
D-CHANNEL PROTOCOL PROCESSOR
Document Type and Number:
Japanese Patent JPS6436148
Kind Code:
A
Abstract:

PURPOSE: To confirm the normal operation according to the protocol based on a D-channel communication protocol by utilizing a signal being the result of inserting a prescribed test data to an information frame of an XID frame for system parameter negotiation having a global terminal identification number as a transmission signal.

CONSTITUTION: A transmission/reception circuit 1 inserts an optional test data to an information field of the XID frame for system parameter negotiation having a global terminal identification number and transmits the result, the XID frame is received as it is by the transmission/reception circuit 1 via a selection circuit 5, and the test data in the reception information frame and the sent test data are compared and collated by the firmware 6. The value of command/response bit in the address field is received with loopback similarly at transmission and reception and it is not required to allocate a terminal identification number in advance to a D-channel protocol processor 8. Thus, it is not required to set the test mode for the purpose of loopback test to the titled processor but the logic to which the titled processor to be followed is tested during the normal communication.


Inventors:
MATSUURA NORITAKA
HISAMATSU HIDENORI
Application Number:
JP19117787A
Publication Date:
February 07, 1989
Filing Date:
July 30, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
(IPC1-7): H04L11/12
Attorney, Agent or Firm:
Naotaka Ide