Title:
A/D変換回路
Document Type and Number:
Japanese Patent JP4345854
Kind Code:
B2
Abstract:
An A/D converter has a series of M delay units through which a pulse signal is transmitted while being delayed in each delay unit by a delay time depending on a level of an analog signal. A unit of the converter latches the pulse signal outputted from each delay unit at N sampling times to hold M×N latched data. Another unit of the converter receives the M×N pieces of latched data as a piece of combined data composed of the latched data arranged in an order corresponding to an arranging order of M×N sampling points in the pulse signal, converts the combined data into numeral data, corresponding to a position of the pulse signal in the delay units, at one time, and produces converted digital data corresponding to the level of the analog signal from the numeral data.
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Inventors:
Tomohisa Terasawa
Takamoto Watanabe
Takamoto Watanabe
Application Number:
JP2007185928A
Publication Date:
October 14, 2009
Filing Date:
July 17, 2007
Export Citation:
Assignee:
株式会社デンソー
International Classes:
H03M1/50
Domestic Patent References:
| JP2003273735A | ||||
| JP2004007385A | ||||
| JP2004357030A | ||||
| JP1251825A | ||||
| JP11088174A |
Attorney, Agent or Firm:
Nagoya International Patent Service Corporation