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Title:
A-D CONVERTER
Document Type and Number:
Japanese Patent JPS5787623
Kind Code:
A
Abstract:

PURPOSE: To reduce error due to noise, etc., by comparing a counter output after being converted into an analog value with an input signal, inputting a clock pulse to a register according to the output of comparison, and completing the measurement when the counter makes full-count.

CONSTITUTION: A counter 4 and a register 12 are cleared and a clock generator 3 generates a clock. This clock is counted by a counter 4, the count value is converted into an analog value with a D/A converter 2 and applied to a comparator 1. A temperature data (b) is applied to the comparator 1 and the register 12 counts the clock until the output of the D/A converter 2 is greater than the temperature data. When the counter 4 makes full-count, a gate 5 is opened and the operation of the clock generator 3 is stopped. If any noise is present, since the comparator 1 only inverts, the error of the register 12 is reduced.


Inventors:
NUKUSHINA HARUNOBU
Application Number:
JP16432380A
Publication Date:
June 01, 1982
Filing Date:
November 21, 1980
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H03M1/46; H03M1/08; H03M1/56; (IPC1-7): H03K13/20
Domestic Patent References:
JPS49102267A1974-09-27