Title:
The DMOS transistor provided with a cavity under a drift field
Document Type and Number:
Japanese Patent JP6073862
Kind Code:
B2
Abstract:
A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
Inventors:
William french
Vladislav Vashchenko
Richard Wendell Hoot
Alexei Sudovnikov
Puni Bora
Peter Jay Hopper
Vladislav Vashchenko
Richard Wendell Hoot
Alexei Sudovnikov
Puni Bora
Peter Jay Hopper
Application Number:
JP2014508559A
Publication Date:
February 01, 2017
Filing Date:
April 26, 2012
Export Citation:
Assignee:
Texas Instruments Japan Ltd.
Texas Instruments Incorporated
Texas Instruments Incorporated
International Classes:
H01L21/336; H01L29/786
Domestic Patent References:
| JP6188438A | ||||
| JP2007123823A | ||||
| JP2002110987A | ||||
| JP2008541421A | ||||
| JP2006173204A | ||||
| JP2007158139A | ||||
| JP2003504875A |
Foreign References:
| US6211551 |
Attorney, Agent or Firm:
Kyozo Katayose
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