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Patent Searching and Data


Title:
DATA BUS MUTUAL CONVERSION SYSTEM
Document Type and Number:
Japanese Patent JPS6455665
Kind Code:
A
Abstract:

PURPOSE: To enable even a 16-bit CPU to access an option board connected to an 8-bit CPU by providing a timing indicating means which indicates the timing when an address signal and a data signal are separated from each other by a separating means.

CONSTITUTION: This data bus compatible system where CPUs different in bit constitution like an 8-bit arithmetic processing unit CPU and a 16-bit are used together is provided with a separating means which separates the multiplexed signal of the address signal and the data signal into the address signal and the data signal and a timing indicating means 7 which indicates the timing of this separation in the separating means 2. For example, multiplexed address signal and data signal outputted from the 16-bit CPU are separated in parallel by the separating means at the timing indicated by the timing indicating means, and therefore, data can be sent to the 8-bit device.


Inventors:
ISHII MASASHI
Application Number:
JP21326587A
Publication Date:
March 02, 1989
Filing Date:
August 27, 1987
Export Citation:
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Assignee:
CANON KK
International Classes:
G06F13/36; G06F13/40; (IPC1-7): G06F13/20
Attorney, Agent or Firm:
Yoshikazu Tani