PURPOSE: To attain the high speed of a writing(storing) operation by providing a buffer means which receives and stores information from a processing means, and a data cache means which receives and stores the information.
CONSTITUTION: When a central processing unit(CPU) 100 executes a storage instruction, access to a data cache 112 is performed for checking a hit. When a cache hit occurs, storage data 110 and 124 and addresses 118 and 120 are written in a storage buffer 128, and the data cache 112 is not updated. The check of the cache and the update of the buffer occur in the same time necessary for a load, and performance can be improved without necessitating any extra time. The buffer 128 has the finite number, and when the buffer 128 is full and the storage is executed, the CPU 100 stops in order to make one or more entries empty. When a cache error occurs, the CPU 100 stops and processes the error.
SUCHIIBUN AARU UNDE
DANIERU RII HARUPERIN
