PURPOSE: To realize a data communication by writing the information written in each RAM arranged in the prescribed address sections in the RAM of the opposite party, between two data processing systems.

CONSTITUTION: In two data processing systems having each independent bus, data is written in a RAM 101 enabling the writing at a prescribed address section from the bus of a first data processing system 100, and at the same time, the address and data is written in an FIFO memory 102. The address and data written and stored in the FIFO memory are read in order of older address and data and are transmitted to a second data processing system 200 via a communication path 1. The signal transmitted to a second data processing system is received by the reception circuit 204 of this system, the signal is decoded into address and data, and this data is written in the address where a RAM 201 enabling the writing at a prescribed address section is received from the bus of this system, mediating between data and the reading and writing from the bus.