PURPOSE: To secure a setup time and hold time between a clock signal and a data signal even when an operation signal speed becomes slow and to improve the reliability of a high-speed operation circuit by dividing input data to plural data lines which are different in phase on a time base by using a clock signal and making cycles of data different from the input data.

CONSTITUTION: The (n) input data lines 1 which are synchronized with an external clock signal 7 are inputted to a data holding circuit part 4. This external clock signal 7 is inputted to a timing generating circuit 3 and converted to (m) timing signal lines 2 which are different in timing. The (n) input data lines 1 are converted to the (m) data lines which are different in timing by (m) timing lines 2 inputted to the data holding circuit part 4 and outputted as m×n internal data lines 5. Then the data are processed by supplying an external clock signal 7 or (m) timing signal lines 2 and m×n internal data lines 5 to an internal circuit 6.