PURPOSE: To recognize a pattern at a high speed by applying (n × 3) pieces of data which are shifted by the 1st-3rd shift registers to an address terminal and then outputting these data in accordance with (n × 3) units of windows corresponding to those (n × 3) pieces of data.
CONSTITUTION: The data to be recognized are applied to the cells 10-12 for each dot and converted via the parallel processing. That is, a 1st shift register 1 applies the input data to the cells 10 and 11 adjacent to each other and at the same time shifts these data in sequence. A 2nd shift register 2 receives data from an adjacent cell 10 and then shifts these data in sequence. Then a 3rd shift register 3 receives data from the adjacent cell 12 opposite to the register 2 and shifts these data in sequence. Furthermore a memory 4 applies (n × 3) pieces of data which are shifted by the registers 1-3 to an address terminal and then outputs the converted data corresponding to those (n ×3) pieces of data. In such a constitution, a pattern is recognized at a high speed.
ASO HIROTOMO
KATSUYAMA YUTAKA
KIMURA MASAYUKI
| JPS52117522A | 1977-10-03 | |||
| JPS5485638A | 1979-07-07 |
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