PURPOSE: To realize a parallel/serial data conversion at high reliability by constituting a selecting circuit so as to selectively operate with delaying by ≥one clock of a clock frequencies nF, and inserting a delay circuit to a signal line at ≥ one of a parallel signal.

CONSTITUTION: The selective timing of a selective circuit S1 is delayed by one clock of the clock frequencies nF, and a delay circuit L having a delay time larger than the one clock of the clock frequencies nF is inserted to the signal line of an input terminal INn of a parallel signal dn. Consequently, the parallel signal dn, is delayed by the delay circuit L, and inputted to a selecting circuit S1 as the parallel signal dn, delayed by one clock of the clock frequencies nF. Thus, the selection of the leading edge part of clock frequencies F is evaded, the selection of the stable condition of the parallel signal is attained, and the highly reliable data conversion in which the unstable output of a serial signal is not generated can be realized.