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Patent Searching and Data


Title:
DATA DECODING SYSTEM
Document Type and Number:
Japanese Patent JPH01103321
Kind Code:
A
Abstract:

PURPOSE: To quicken the restoring speed by deciding the quantity of data in the unit of a maximum code length by a comparator to identify the code length of a variable length code to be converted.

CONSTITUTION: Data by a variable length code are inputted synchronously with a clock serially into a shift register and subject to 4-bit parallel processing in a latch circuit 11 by a latch output of a control circuit 12. The data processed in parallel is converted into a decoded code by a code conversion table 2. On the other hand, the 4-bit parallel data of the circuit 11 is compared with constants C1=0111, C2=1011 by a couple of magnitude comparators 30, and when the 4-bit data D is less than the constant C1, the output of the comparator at the left side as shown in figure goes to '1' and when the 4-bit data D are less than the constant C2, the output of both the comparators 30 goes to '1'. Thus, the circuit 12 can identify the code length as 2-bit length when the output of both the comparators 30 is '10', as 3-bit length when '11' and as 4-bit length when '00'. Thus, the composition of the next data is attained early and the restoring speed is improved.


Inventors:
YONETANI AKIHIKO
SUGIURA HAJIME
Application Number:
JP26107687A
Publication Date:
April 20, 1989
Filing Date:
October 16, 1987
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03M7/40; (IPC1-7): H03M7/40
Attorney, Agent or Firm:
Akira Yamatani



 
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