PURPOSE: To decrease a chip in area in case of circuit integrtion by applying clock signals different in phase to data latch circuits in cascade connection such as clocked inverters so as to decrease the number of elements per bit.

CONSTITUTION: Seven CMOS clocked inverters 21∼27 are conneted in cascade, input data 30 is fed to an inverter 21 of the 1st stage and a data 38 is outputted from the inverter 27 of the final stage. Clock signals 7∼1 having different phase and their inverted signals are fed to the inverters 21∼27 respectively from the 2st stage to the final stage. Then the inverters 21∼27 are established from the final stage to the first stage sequentially and the 7 inverters 21∼27 attain the storage/delay of data for 6-bit's share. Thus, the number of elements per bit is decreased and the chip area at circuit integration is decreased.