PURPOSE: To demodulate the data concerned from a data modulating signal whose pulse width is modulated in a boundary of '0' and '1' bits of the data.
CONSTITUTION: A data modulating signal DM is inverted by an inverter 1 together with a shift register 3a driven by a clock signal 0 being asynchronous thereto, and supplied to a shift register 3b, as well, driven by a clock signal 1. Also, the shift registers 3a, 3b are cleared for an 'L' period of the respective inputs. The shift register 3a generates an output Pa in an 'H' period of the data modulating signal DM being longer than its transfer time, and the shift register 3b generates the output Pa in an 'L' period of the data modulating signal DM being longer than its transfer time. A flip-flop circuit 4 is reset by the output Pa, and set by an output Pb. In such a way, from the flip-flop circuit 4, original data DATA is obtained.
KATAYAMA YOSUKE
NISHIZONO KAZUNORI
KOKUBU MASATOSHI
IEGI TOSHIATSU
TAKEUCHI TAKASHI
FUJITSU LTD
NTT DATA TSUSHIN KK