Title:
DATA DEMODULATION CIRCUIT AND ITS METHOD
Document Type and Number:
Japanese Patent JP3426191
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a method and a device capable of simply substituting a circuit realized by miniaturized digital logic for a PLL circuit.
SOLUTION: In order to measure a pulse interval for encoding data information by utilizing a high frequency signal always existing in a current system as a logic clock independent of a coded data signal, an edge detector 10 generates an edge pulse when the coded signal is transited. A time counter 12 counts the cycle of logic clocks between two succeeding edge pulses. A window comparator 16 compares a prescribed counting range with the cycle count value and generates time result signals 1t, 2t, 3t, >3t, etc. A decoder state machine 20 samples a time result at each edge pulse and activates a decoded data bit (0 or 1), a data clock frame start signal or NO signal.
Inventors:
Gottfried Andreas Goldrian
Gerhard Jills
Gerhard Jills
Application Number:
JP2000171485A
Publication Date:
July 14, 2003
Filing Date:
June 08, 2000
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H03M5/12; H03D3/00; H04B14/04; H04L7/02; H04L7/033; H04L27/156; (IPC1-7): H03M5/12; H03D3/00; H04B14/04; H04L7/033
Domestic Patent References:
| JP253327A | ||||
| JP5227035A | ||||
| JP6444625A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)
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