PURPOSE: To provide a data input/output device which improves efficiency for transferring data between two bus systems at different transfer speed.

CONSTITUTION: A FIFO memory state judge part 10 receives a FIFO memory write address WAD and a FIFO memory read address RAD outputted from a write address pointer 3 and a read address pointer 4 and judges the internal state of a FIFO memory 1 from these address values. In the case of writing data from the side of a bus DA at higher data transfer speed, a data transfer request REQ is generated from a data transfer request control part 11 when the state of margin for writing over prescribed number of data in the FIFO memory 1 is detected, and the data transfer request REQ is stopped when the full state of the FIFO memory 1 is detected.