DATA ERASING METHOD, AND MEMORY DEVICE HAVING DATA ERASURE CIRCUIT USING THE METHOD

Title:

DATA ERASING METHOD, AND MEMORY DEVICE HAVING DATA ERASURE CIRCUIT USING THE METHOD

Document Type and Number:

Japanese Patent JP2005038504

Kind Code:

A

Abstract:

To provide a data erasing method for shortening a time necessary for data erasure without increasing power consumption for the data erasure, and a memory device having a data erasing circuit using the data erasure method.

In the data erasing method for erasing data stored by discharging charges stored in a floating gate by applying an erasing voltage between a semiconductor substrate and a control gate, the potential of the semiconductor substrate side is increased while the control gate is kept in a floating state, and then the potential of the control gate is set to a predetermined potential, and thus an erasing voltage is applied between the semiconductor substrate and the control gate. The potential of the control gate is set to the predetermined potential by taking a predetermined time for lowering so that the increased potential of the semiconductor substrate side is not lowered.

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Inventors:

SEKIMOTO SHUNJI
NAMISE TOMOHIRO

Application Number:

JP2003274113A

Publication Date:

February 10, 2005

Filing Date:

July 14, 2003

Export Citation:

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Assignee:

SONY CORP

International Classes:

G11C16/02; G11C16/04; G11C16/14; H01L21/8247; H01L27/10; H01L27/115; H01L29/423; H01L29/788; H01L29/792; (IPC1-7): G11C16/02; G11C16/04; H01L21/8247; H01L27/10; H01L27/115; H01L29/788; H01L29/792

Attorney, Agent or Firm:

Kenichiro Matsuo

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