PURPOSE: To facilitate the replacement of data within a time slot or the replacement of the time slot by controlling read-out data by writing serial plural time slot data in a memory and reading it through an address control memory.

CONSTITUTION: Plural time slot data from a PS converter 1 are written in the memory 3 by an address from a sequential address generation circuit 2. On the other hand, in the address control memory 6, the address of a bit to be converted is written as a random address in the address of the bit desired to convert among the bits written in the memory 3, and an H-level is written is the address of the bit to be inverted. Then, the memory 6 is read out by the address of the circuit 2, and the address is supplied as a read-out address to the memory 3, and the H-level is supplied as a control signal for inversion to an exclusive OR circuit 4, and the data of address conversion and of the designated bit are inverted and outputted from the SP converter 5, and the data whose format is converted so that the data within the time slot or the time slot is replaced is easily outputted.