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Title:
DATA INPUT CIRCUIT OF SYNCHRONOUS-TYPE SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP3945793
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To enable a quick data writing operation by a method wherein one signal is selected among the 1st and 2nd internal strobe signals of a 1st edge detector or the 1st and 2nd internal clock signals of a 2nd edge detector by a selective control signal applied from an external device.
SOLUTION: When an edge detector 200 detects the rising edge of an external clock signal CLK, it generates a 1st internal clock signal &phiv CLK1 and, when it detects the falling edge of the external clock signal CLK, it generates a 2nd internal clock signal &phiv CLK2. Registers 202a and 202b are synchronized with the inputted 1st and 2nd internal clock signals &phiv CLK1 and &phiv CLK2 respectively and store odd number order data D1, D3... and even number order data D2, D4... of an input data string DINDM inputted from an external device respectively. Writing drivers 204a and 204b are activated by a timing control circuit 308 and transmit corresponding data pairs D1-D4 one after another. Successively, a column decoder 209 is also activated in the same way to select a column corresponding to an address.


Inventors:
Lee Sadafumi
Application Number:
JP6824198A
Publication Date:
July 18, 2007
Filing Date:
March 18, 1998
Export Citation:
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Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C11/413; G11C7/10; G11C11/401; G11C11/407; G11C11/409; G11C11/4093; (IPC1-7): G11C11/413; G11C11/409; G11C11/407
Domestic Patent References:
JP6267279A
JP8180678A
JP6076566A
JP10199239A
JP7093970A
JP9106671A
JP61039297A
JP10040678A
JP9063262A
JP8221981A
JP9055089A
JP7169263A
JP7036773A
Attorney, Agent or Firm:
Makoto Hagiwara