PURPOSE: To attain miniaturization and to obtain a data latch circuit to be easly designed by constituting the data latch circuit of logic circuits only such as FFs and exclusive logic circuits without use of a multiplier circuit including the resistor and the capacitor.

CONSTITUTION: A data FF 4 fetches a data IN signal at the time of rising a clock signal CK and outputs a Q output A. Moreover, a data FF 5 fetches the signal IN at the time of falling the clock signal CK and outputs a Q output B. Output signals A, B are inputted to an exclusive OR circuit 7, which exclusively ORs the signals A, B to output a signal E. A data FF 6 inputs the signal IN from a terminal 1 to a data input terminal D and inputs a signal E from the circuit 7 to a clock input terminal C. Then the data FF 6 fetches the signal IN at the time of rising the signal E to output an output signal OUT with nearly equal pulse width to that of the signal IN via a data output terminal 3. Since the latch circuit is constituted of logic circuits only, the size of the semiconductor integrated circuit is made small and the design is facilitated.