Title:
DATA OUTPUT BUFFER
Document Type and Number:
Japanese Patent JP3049198
Kind Code:
B
Abstract:
PURPOSE: To prevent latching up by forming an N-well guard ring widely in a substrate between a P-well and an N-well, and so on, and preventing monority carriers from moving from an NMOS transistor to the N+ pickup region of a PMOS transistor of a PMOS transistor effectively.
CONSTITUTION: This buffer has an NMOS transistor formed in the P-well 2 of a P-type substrate 1 and composed of a first and a second N+ regions 23, 23 and a gate electrode 21, and a PMOS transistor formed in the N-well 3 of the P-type substrate 1, and composed of a first and a second P+ regions 32, 33 and a gate electrode 31. Besides, it has input/output pads 5 connected to the second N+ region 23 of the NMOS transistor, and to be connected to the first P+ region 32 of the PMOS transistor. Moreover, it has an N-well guard ring 4 formed between the P-well 2 and the N-well 3, being separated from the P-well 2 and the N-well 3 at specified distances.
Inventors:
Kim, Pil Jong
Application Number:
JP1995000143042
Publication Date:
March 24, 2000
Filing Date:
June 09, 1995
Export Citation:
Assignee:
HYUNDAI ELECTRON IND CO LTD
International Classes:
B03C3/62; B03C7/04; B05B5/03; B05B5/043; B05B5/08; B41J2/415; B65G54/02; G03G15/08; H01T19/00; H05F3/04; (IPC1-7): H01L21/82; H01L27/04; H01L21/822
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