PURPOSE: To obtain a data processing circuit which surely synchronizes a write/ read signal inputted to a memory and an address signal inputted to the memory with each other.

CONSTITUTION: An actual write signal the inverse of MCW of a memory A is generated by a flip flop 8 and gates 9 and 17, and a write reference signal the inverse of W, a task signal TSK, and the output of the gate 9 are inputted to the gate 17 to generate the write signal the inverse of MCW. A count-down enable signal CDE of an address down counter 10 is generated by a flip flop 11 and an AND gate 12, and the write signal the inverse of MCW of the memory A is inputted to a clock terminal CK of the flip flop 11 to synchronize the count down enable signal CDE with the write signal the inverse of MCW.