PURPOSE: To reduce the operation circuits and shorten the access time by carrying out only the address operation at first, after the access to the column, and performing the row address operation to make row access.

CONSTITUTION: The operation circuit ALU carries out the column address computation as a first operation and transmits the column address to the main memory device MM through the bus BS. The main memory device MM latches the column address and decodes by the decoder to make column access. Then, the switch circuit SWC selects the second operation data from the memory ROM and sets it at the register CMIR and decoded by the decoder DEC to input to the operation circuit ALU. By performing the row address computation, the row address is fed to the main memory device MM through the bus BS and the row access is performed by the similar means.