PURPOSE: To shorten the time from instruction read to operand read to improve the performance of a processing device, by providing an adder, which outputs a logical address, and a generating means which combines the output of an address conversion mechanism and a lower bit part of the logical address to generate the whole of an actual address.

CONSTITUTION: When the value of a base register number 2 of an instruction set to an instruction register 1 is (1) and the value of an address displacement 3 is 900 in the hexadecimal numeration, contents of the base register number 2 are transmitted to a general register 4 and a high-speed address conversion buffer 11, and contents of a base register and an actual address value are read out. Since it cannot be discriminated at this time whether the actual address value is 00008 or 00009, both values are outputted. The value of the general register 4 is inputted to an address adder 5 to perform address addition. The value of a carry of upper 20 bits of the address is transmitted to the high-speed address conversion buffer 11 in the course of address addition, and value 00008 for the carry is selected as the actual address by a selecting circuit 14.