PURPOSE: To prevent the occurrence of a communication error owing to the software overhead of protocol conversion CPU by synchronizing high-order communication with low-order communication and preventing the simultaneous interruption of high-order communication and low-order communication in protocol conversion CPU.

CONSTITUTION: When protocol conversion μ-CPU 3A receives polling from high-order CPU 1 and receives data for t01 time in high-order communication, it immediately transmits appropriate data to CPU 1 for t02 time. When polling in high-order communication terminates by the transmission, CPU 3A shifts a system to low-order communication and starts polling to respective low-order CPU 5. Namely, data is transmitted for t11 time and polling is performed to initial CPU 5, whereby data from CPU 5 is received for t12 time. Then, polling is performed to CPU 5 and data from it is received for t22 time. Then, polling to n-th low-order CPU 5 is performed in order and data from last CPU 5 is received for ta2 time.